Several trends exist presently in the semiconductor and electronics industry. Devices are continually getting smaller, faster and requiring less power. A reason for these trends is that more personal devices are being fabricated that are relatively small and portable, thereby relying on a battery as their primary supply source. For example, cellular phones, personal computing devices, and personal sound systems are devices in great demand in the consumer market. In addition to being smaller and more portable, personal devices are requiring more computational power and speed. In light of all these trends, there is an ever increasing demand in the industry for smaller and faster transistors used to provide the core functionality of the integrated circuits used in these devices.
Accordingly, in the semiconductor industry there is a continuing trend toward manufacturing integrated circuits (ICs) with higher densities. To achieve high densities, there has been and continues to be efforts toward scaling down dimensions (e.g., at submicron levels) on semiconductor wafers, which are generally produced from bulk silicon. In order to accomplish such high densities, smaller feature sizes, smaller separations between features and more precise feature shapes are required in integrated circuits (ICs) fabricated on small rectangular portions of the wafer, commonly known as dies. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, as well as the surface geometry of various other features (e.g., corners and edges). The scaling-down of integrated circuit dimensions can facilitate faster circuit performance and/or switching speeds, and can lead to higher effective yield in IC fabrication by providing more circuits on a die and/or more die per semiconductor wafer.
The process of manufacturing integrated circuits typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit can be formed on a single wafer. This process can create electrically active regions in and on the semiconductor wafer surface. In MOS transistors, for example, a gate structure is created, which can be energized to establish an electric field within a semiconductor channel, by which current is enabled to flow between a source region and a drain region within the transistor. The source and drain regions facilitate this conductance by virtue of carefully tailored doping to form positively doped (p) or negatively doped (n) regions around the channel.
As device sizes continue to shrink, however, capacitive effects may become noticeable and/or problematic. There are a number of extrinsic capacitances associated with a MOS transistor. For example, ion implantation is utilized to create the source and drain regions, as well as source and drain extension regions in the transistor. A high temperature anneal is subsequently employed to activate the implanted dopants. This high temperature anneal can cause lateral diffusion of the implanted species such that some of the dopants can migrate under the gate structure.
These overlap regions can give rise to “overlap capacitances” since the gate structure includes a conductive layer overlying a dielectric material, and the dielectric material, in turn, is situated over the diffused conductive dopants. The value of the overlap capacitance depends upon the area or degree of overlap between the gate structure and the diffused dopants, among other things. Accordingly, as scaling occurs and the size of the gate structure is reduced, the percentage of overlapping area increases and the overlap capacitance increases, becoming a larger percentage of the total overall transistor capacitance. This can result in a reduction in transistor and IC performance, such as by reducing or otherwise adversely affecting transistor switching speeds.
Accordingly, improved techniques for fabricating densely packed semiconductor devices would be desirable. More particularly, it would be desirable to fabricate semiconductor devices in a manner that reduces overlap capacitances and allows for faster switching speeds.